Solders are special composition metals (known as alloys) that, when in the presence of flux, melt at relatively low temperatures (120-450° C.). The most commonly used solders contain tin and lead as base components. Many alloy variations exist that include two or more of the following metallic elements: tin (Sn), lead (Pb), silver (Ag), bismuth (Bi), antimony (Sb) and copper (Cu). Solder works by melting when it is heated, and bonding (wetting) to metallic surfaces. The solder forms a permanent intermetallic bond between the metals joined, essentially acting like a metal “glue.” In addition to providing a bonding function, solder joints also provide an electrical connection between soldered components and a heat transfer path. Solders are available in many forms including paste, wire, bar, ribbon, preforms and ingots.
Many high-density integrated circuits (ICs), such as microprocessors, graphics processors, microcontrollers, and the like are packaged in a manner that use of a large number of I/O lines. Common packaging techniques employed for this purpose include “flip chip” packaging and ball grid array (BGA) packages. Both of these packaging techniques employ solder connections (joints) for each I/O line (e.g., pin or ball). In conjunction with the every-increasing density of complex ICs, a corresponding increase in the I/O connection density of flip chip and BGA has occurred. As a result, the solder joints employed in the packages have had to be reduced in size.
More specifically, Flip Chip (FC) is not a specific package (like SOIC), or even a package type (like BGA). Flip chip describes the method of electrically connecting the die to the package carrier. The package carrier, either substrate or leadframe, then provides the connection from the die to the exterior of the package. In “standard” packaging, the interconnection between the die and the carrier is made using wire. The die is attached to the carrier face up, then a wire is bonded first to the die, then looped and bonded to the carrier. Wires are typically 1-5 mm in length, and 25-35 μm in diameter. In contrast, the interconnection between the die and carrier in flip chip packaging is made through a conductive “bump” that is placed directly on the die surface. The bumped die is then “flipped over” and placed face down, with the bumps connecting to the carrier directly. A bump is typically 70-100 μm high, and 100-125 μm in diameter.
The flip chip connection is generally formed one of two ways: using solder or using conductive adhesive. By far, the most common packaging interconnect is solder, high 97Pb-3Sn at die side and attached with eutectic Pb—Sn to substrate. The solder bumped die is attached to a substrate by a solder reflow process, very similar to the process used to attach BGA balls to the package exterior. After the die is soldered, underfill is added between the die and the substrate. Underfill is a specially engineered epoxy that fills the area between the die and the carrier, surrounding the solder bumps. It is designed to control the stress in the solder joints caused by the difference in thermal expansion between the silicon die and the carrier, as described in further detail below. Once cured, the underfill absorbs much of the stress, reducing the strain on the solder bumps, greatly increasing the life of the finished package. The chip attach and underfill steps are the basics of flip chip interconnect. Beyond this, the remainder of package construction surrounding the die can take many forms and can generally utilize existing manufacturing processes and package formats.
Recently, the European Union has mandated that no new products sold after May 31, 2003 contain lead-based solder. Other counties and regions are considering similar restrictions. This poses a problem for manufactures of IC products, as well as for other industries that employ soldering processes during product manufacture. Although many Pb-free solders are well-known, these solders have properties that make them disadvantageous when compared with lead-based solders, including reduction in ductility (plasticity). This is especially problematic in flip-chip and BGA assembly processes.
Owing to active R & D efforts, substantial progress toward a full transition to Pb-free soldering technology has been made recently. At present, the leading candidate solders are near-ternary eutectic Sn—Ag—Cu alloys for various soldering applications. The near-eutectic ternary Sn—Ag—Cu alloys yield three phases upon solidification, β-Sn, Ag3Sn and Cu6Sn5. During solidification, the equilibrium eutectic transformation is kinetically inhibited. While the Ag3Sn phase nucleates with minimal undercooling, the β-Sn phase requires a typical undercooling of 15 to 30° C. for nucleation. As a consequence of this disparity in the required undercooling, large, plate-like Ag3Sn structures can grow rapidly within the liquid phase, during cooling, before the final solidification of solder joints. When large Ag3Sn plates are present in solder joints, they may adversely affect the mechanical behavior and possibly reduce the fatigue life of solder joints by providing a preferential crack propagation path along the interface between a large Ag3Sn plate and the β-Sn phase. Further problems common to Sn—Ag—Cu solders include ILD (inner layer dielectric) cracking and pad peel off at the substrate for flip chip assemblies, and pad peel off at the BGA side for BGA packages.